High-Level Synthesis tools / an overview
28-09-2010 :: Campus De Nayer, Lessius, Belgium

Organizer: Campus De Nayer, Lessius

The capacity of silicon doubles every two year, according to Moore’s law, resulting in digital designs with an ever growing complexity. Traditional hardware design at Register Transfer Level (RTL), written by hand using a hardware description language (HDL), becomes too time-consuming.

High-levels synthesis (HLS) uses methods and tools in order to raise the design productivity and quality. The design entry starts from specifications at a higher level of abstraction (algorithmic / behavioral), independent of the RTL-architecture, which allows a better management of the system design complexity. HLS tools automatically generate verified RTL-architectures that are optimized to various design implementation options (area, performance, power), improving the quality of the result and reducing the overall design cycle.

In the Fast-ProMoCo project (IWT-TETRA), commercial HLS-tools were evaluated based on common criteria: learning curve, level of abstraction, verification time, capabilities and efficiency of the synthesis process. Demonstrators were build for the same test-case.

During this seminar the results of the Fast-ProMoCo project will be described, vendors of HLS-tools present their products, users will share their experience.

http://www.fast-promoco.be/

 

Contact person:

Jan Meel

jan.meel@denayer.wenk.be

tel.:+32 15 31 69 44










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